1. Field of the Invention
This invention relates to power management within computer systems and more particularly to a system and method for controlling a peripheral bus clock signal.
2. Description of the Relevant Art
An on-going developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems.
Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMU's). One specific power reduction technique involves the capability of stopping clock signals that drive inactive circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals associated with the inactive circuit portions. By turning off "unused" clock signals that drive inactive circuit portions, overall power consumption of the system is decreased. A similar technique involves the capability of reducing the frequency of clock signals that drive circuit portions during operating modes which are not time critical.
Although the capability of stopping "unused" clock signals has been generally successful in reducing power consumption, the technique has generally not been applied to clock signals that drive peripheral buses having alternate bus masters connected thereto. The reason for this limitation is best understood from the following example.
FIG. 1 is a block diagram that illustrates a computer system 10 including a microprocessor (CPU) 12, a system memory 14, a bridge/memory controller 16, and a bus interface and arbiter unit 18. A CPU local bus 20 couples the microprocessor 12 to bridge/memory controller 16 and bus interface and arbiter unit 18. A system memory bus 22 couples system memory 14 to bridge/memory controller 16. An alternate bus master 26 labeled "Master1" and a second alternate bus master 28 labeled "Master2" are coupled to the bus interface and arbiter unit 18 through a peripheral bus 30. A slave device 31 is similarly coupled to bus interface and arbiter unit 18 through peripheral bus 30.
When alternate bus master 26 requires mastership of peripheral bus 30, a request signal labeled REQ1 is asserted by the alternate bus master 26 and is detected by bus interface and arbiter unit 18. If mastership of the bus is granted in accordance with the internal arbitration logic, the bus interface and arbiter unit 18 asserts a grant signal labeled GNT1 and, accordingly, alternate bus master 26 attains mastership of peripheral bus 30 and may execute the desired cycle.
In the system of FIG. 1, the request signal REQx (i.e., REQ1 or REQ2) must be asserted by the associated alternate bus master synchronous to the peripheral bus clock signal CLK. This requirement is specified by several prevalently utilized peripheral bus standards, such as the PCI bus standard. As a result of the requirement, systems employing such peripheral bus standards are designed such that the peripheral bus clock signal CLK is always turned on, thereby allowing an alternate bus master to generate a synchronous request signal. In such systems, however, power is wasted when the peripheral bus is idle.
An additional hindrance to the employment of clock-stopping (or clock-slowing) power reduction techniques for peripheral buses arises since slave devices may require a clock signal beyond the end of a peripheral bus cycle. For example, additional clock cycles may be required at the completion of a peripheral bus cycle for slave device 31 to empty an internal FIFO. If the clock signal were stopped during such a situation, the performance of the system as well as the integrity of data may be adversely affected.
Still another problem associated with stopping or slowing a peripheral bus clock signal for power management purposes is that if the peripheral device is incapable of restarting the peripheral bus clock signal or does not receive a clock edge within a given time, the external bus master may be stalled or may lose data. As a result, the performance of the system may be degraded or the integrity of data may be adversely affected. Since data integrity is crucial within any computer system and since conventional peripheral bus masters are typically incapable of controlling an associated peripheral bus clock signal, such conventional bus master devices may not be compatible with a computer system wherein a peripheral clock signal is stopped or slowed for power management. Consequently, the backwards compatibility of such a computer system with conventional peripheral devices may be limited.